“Charging damage” or “plasma damage” may degrade gate oxide of complementary metal oxide semiconductor (CMOS) devices during wafer processing. During certain process steps, charge may be collected by circuit electrodes exposed during that process step, which may induce currents to flow in the partially formed circuit. If a large driving force is created that forces a current to flow through the gate oxide, then permanent damage may occur. In traditional CMOS logic circuits, a gate-protection diode may be coupled between a gate and a substrate. However, for isolated FET elements, such as floating body or body contacted FET elements, the substrate is isolated from the FET elements, thereby precluding use of traditional gate-protection diodes. Floating body or body contacted FET elements may be used to form RF switches, in which each FET element needs good RF isolation from adjacent devices for good RF performance, such as low harmonic distortion. An RF switch may have one or more large metal pads, which may be used for providing connections to the RF switch. However, such large metal pads may also inadvertently function as a “charging antenna,” which may collect damaging energy due to wafer processing. It may be possible to use a remote gate-protection diode that is coupled between the gate and another node of the isolated FET via metallic interconnects to limit the voltage across the gate oxide. However, such a diode placement would typically introduce RF coupling to adjacent circuits, thereby degrading harmonic performance of the RF switch. Thus, there is a need for a technique to protect the gate oxides of isolated FET elements during certain steps of wafer processing that doesn't degrade performance of devices formed from the isolated FET elements, such as RF switches.